Job Description

Verification Engineer
Eclaro is looking for a Verification Engineer for an opportunity for our client in SAN JOSE, CA.
Job Duties:
  • Develop SystemVerilog and UVM verification environments for block-level and top-level modules
  • Build and maintain verification plans
  • Write and run test cases for RTL simulation
  • Debug functional errors in the RTL by working closely with design engineers
  • Define and implement functional coverage and constrained random verification methods
  • Develop and improve design verification environment to ensure coverage closure

Basic Skills, clearances and other elements required, in order of importance, and number of years experience, where applicable, in each skill:
1) Experience with SystemVerilog with assertions, UVM test benches
2) Experience with C and C++ and scripting languages
3) Experience with linux environment
4) Familiarity with industry standard ASIC EDA tools, including logic simulators, and debuggers
5) Familiarity with formal verification and linters
6) Compliance with Export Regulations

Other Skills Desired, Years in each skill, where applicable:
At least 3 year experience in any of the following: SystemVerilog, UVM, SystemC, Verilog or VHDL
At least 1 year in C++/Python and Object Oriented Methodology

Equal Opportunity Employer: Eclaro values diversity and does not discriminate based on Race, Color, Religion, Sex, Sexual Orientation, Gender Identity, National Origin, Age, Genetic Information, Disability, Protected Veteran Status, or any other legally protected group status.

Application Instructions

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