Job Description

RTL/Logic Design Engineer
JobDiva # 20-07433

Eclaro is looking for a RTL/Logic Design Engineer for our client in San Jose, CA.  

Eclaro’s client is a major technology firm with a prominent presence in large and fast-growing markets, providing products and services that enable businesses and economies to thrive.  If you’re up to the challenge, then take a chance at this rewarding opportunity!

  • RTL coding of circuit, block, and top-level modules
  • Simulation, logic debugging, and verification
  • Timing closure
  • Power optimization
  • Synthesis and placement-driven synthesis
  • Scripting

  • At least 5 years chip design experience with functional and structural SystemVerilog
  • Proficient at running industry standard ASIC EDA tools, including logic simulators, synthesis, timing closure, and power optimization
  • Ability to work in an integrated team environment
  • Ability to design from a high-level specification

Required Experience:
  • At least 10 years experience in any of the following: SystemVerilog, Verilog, or VHDL including simulation and timing closure

If hired, you will enjoy the following Eclaro Benefits:
  • 401k Retirement Savings Plan administered by Merrill Lynch
  • Commuter Check Pretax Commuter Benefits
  • Eligibility to purchase Medical, Dental & Vision Insurance through Eclaro

If interested, you may contact:
Carlo Flores
Carlo Flores | LinkedIn

Equal Opportunity Employer:
Eclaro values diversity anddoes not discriminate based onRace, Color, Religion, Sex, Sexual Orientation, Gender Identity, National Origin, Age, Genetic Information, Disability, Protected Veteran Status, or any other legally protected group status.


Application Instructions

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