Job Description

RTL/Logic Design Engineer
Eclaro is looking for a RTL/Logic Design Engineer for an opportunity for our client in SAN JOSE, CA.
Job Duties:
RTL coding of circuit, block, and top-level modules
Simulation, logic debugging, and verification
Timing closure
Power optimization
Synthesis and placement-driven synthesis

Basic Skills, clearances and other elements required, in order of importance, and number of years experience, where applicable, in each skill:
1) Chip design experience with functional and structural SystemVerilog
2) Familiarity with industry standard ASIC EDA tools, including logic simulators, synthesis, timing closure, and power optimization
3) Compliance with Export Regulations

Other Skills Desired, Years in each skill, where applicable:
At least 3 year experience in any of the following: SystemVerilog, Verilog, or VHDL--including simulation and timing closure
At least 1 year in Scripting, Tcl and Python preferred
Equal Opportunity Employer: Eclaro values diversity and does not discriminate based on Race, Color, Religion, Sex, Sexual Orientation, Gender Identity, National Origin, Age, Genetic Information, Disability, Protected Veteran Status, or any other legally protected group status.

Application Instructions

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