Job Description

Hardware Physical Chip Design Engineer Tools/Process Expert
Job Number: 20-07439
 
Eclaro is looking for a Hardware Physical Chip Design Engineer Tools/Process Expert for our client in San Jose, CA. 
 
Eclaro’s client is a major technology firm with a prominent presence in large and fast-growing markets, providing products and services that enable businesses and economies to thrive.  If you’re up to the challenge, then take a chance at this rewarding opportunity!
 
Qualifications:
  • Multiple successful tapeouts at lower-node technologies (using FinFETs at 14nm nodes and/or below)
  • Prior experience and understanding of GF 12LP/14LPP process or similar (rules, settings, techfiles)
  • At least 6 years’ experience with Cadence tools (must know Innovus, Virtuoso, Genus)
  • Sign-off expertise in DRC/LVS/PEX using Cadence tools
  • At least 3 years TCL and SHELL scripting
  • Extensive experience with multiple Cadence EDA tools, tool administration, and flow automation;
  • Synthesis (including PLE) and formal equivalence checking;
  • RTL, gate-level and transistor-level simulations and debugging.
 
Skills:
  • 3 years of Python/Perl scripting.
 
If hired, you will enjoy the following Eclaro Benefits:
  • 401k Retirement Savings Plan administered by Merrill Lynch
  • Commuter Check Pretax Commuter Benefits
  • Eligibility to purchase Medical, Dental & Vision Insurance through Eclaro
 
If interested, you may contact:
Eileen Sares
esares@eclaro.com
646-755-9301
Eileen Sares | LinkedIn
 
Equal Opportunity Employer:
Eclaro values diversity and does not discriminate based on Race, Color, Religion, Sex, Sexual Orientation, Gender Identity, National Origin, Age, Genetic Information, Disability, Protected Veteran Status, or any other legally protected group status.

Application Instructions

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