Job Description

Task Description:
Candidates are expected to create/modify/script Physical Design tool flows; as well as perform synthesis, physical design, clock-tree design, timing closure, power/performance/area optimizations and signoff based RTL.

Required skills/Level of Experience:
  • Senior Physical Design Engineer.
Required Expertise:
  • Multiple successful tapeouts at lower-node technologies (using FinFETs at 14nm nodes and/or below)
  • At least 4 years experience with Cadence tools in the areas of physical design, including synthesis, LEC, floorplanning, hierarchical clock-tree creation, Place and Route, power grid creation, hierarchical integration, DFM, Signoff
  • Experience with 3rd party IP-s, integration of IP into the design and IP testing
  • Ability to perform and understand results of STA, timing closure and timing signoff
  • Extensive experience with power analysis, power optimizations and power signoff
  • At least 3 years TCL and SHELL scripting
Ideal candidates will have additional expertise in all of the following areas:
  • Extensive experience with multiple Cadence EDA tools, tool administration, and flow automation;
  • In-depth understanding of memory structures, memory testing and integration;
  • Synthesis (including PLE) and formal equivalence checking;
  • Power/Performance/Area analysis and optimizations;
  • RTL, gate-level and transistor-level simulations and debugging;
Additional Preferred Skills:
  • 3 years of Python scripting;
  • Experience with DFT implementation and integration.
  • PCIe IP integration.
Equal Opportunity Employer:Eclaro values diversity anddoes not discriminate based onRace, Color, Religion, Sex, Sexual Orientation, Gender Identity, National Origin, Age, Genetic Information, Disability, Protected Veteran Status, or any other legally protected group status.

Application Instructions

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