Job Description

Required skills/Level of Experience :
  • Experience with SystemVerilog with assertions, UVM test benches
  • Experience with C and C++ and scripting languages
  • Experience with linux environment
  • Familiarity with industry standard ASIC EDA tools, including logic simulators, and debuggers
  • Familiarity with formal verification and linters
    Nice to have skills:
  • At least 3 year experience in any of the following: SystemVerilog, UVM, SystemC, Verilog or VHDL
  • At least 1 year in C++/Python and Object Oriented Methodology
  • Experience with DFT
  • Experience with the simulation and verification of a system including 3rd party IP

Application Instructions

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