Job Description

Job Duties:
Job Duty 1 - Understanding and debugging SDC timing constraints both at the block and chip level.
Job Duty 2 Assist in generating ETMs (Extracted Timing Models).
Job Duty 3 Assist Physical Designers on running static timing analysis tools in Innovus.
Job Duty 4 Lead the effort in running static timing analysis in Tempus (i.e. graph-based and path-based analysis), at the block and Chip level, using distributed timing (DSTA) for the Chip level.
Job Duty 5 Facilitate generating and parsing timing reports via scripts to more effectively identify timing fails.
Job Duty 6 Assist in coming up with fixes in the form of PD scripts and or tempus ECOs for any timing problems.
Job Duty 7 Assist in generating back-annotated SDF files, used for simulations and detailed power analysis.

Basic Skills, clearances and other elements required, in order of importance, and number of years experience, where applicable, in each skill :

1) Refer to Job duties above (i.e. all tools necessary to close timing on a complex ASIC).

2) Other: Strong verbal and written communication skills required.


Other Skills Desired, Years in each skill, where applicable:

Extensive experience as an Electrical / Computer Engineering, 5 years

Equal Opportunity Employer: E claro values diversity anddoes not discriminate based onRace, Color, Religion, Sex, Sexual Orientation, Gender Identity, National Origin, Age, Genetic Information, Disability, Protected Veteran Status, or any other legally protected group status.

Application Instructions

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